PLLSTEN0=0, PLLCLKEN0=0, PLLREFSEL0=0, PRDIV0=0
MCG Control 5 Register
PRDIV0 | PLL0 External Reference Divider 0 (0): Divide Factor is 1 1 (1): Divide Factor is 2 2 (2): Divide Factor is 3 3 (3): Divide Factor is 4 4 (4): Divide Factor is 5 5 (5): Divide Factor is 6 6 (6): Divide Factor is 7 7 (7): Divide Factor is 8 |
PLLSTEN0 | PLL0 Stop Enable 0 (0): MCGPLL0CLK and MCGPLL0CLK2X are disabled in any of the Stop modes. 1 (1): MCGPLL0CLK and MCGPLL0CLK2X are enabled if system is in Normal Stop mode. |
PLLCLKEN0 | PLL Clock Enable 0 (0): MCGPLL0CLK and MCGPLL0CLK2X are inactive. 1 (1): MCGPLL0CLK and MCGPLL0CLK2X are active. |
PLLREFSEL0 | PLL0 External Reference Select 0 (0): Selects OSC0 clock source as its external reference clock. 1 (1): Selects OSC1 clock source as its external reference clock. |